SN74AUC2G04 dual inverter gate sces437a ? april 2003 ? revised june 2003 1 post office box 655303 ? dallas, texas 75265 available in the texas instruments nanostar ? and nanofree ? packages optimized for 1.8-v operation and is 3.6-v i/o tolerant to support mixed-mode signal operation i off supports partial-power-down mode operation sub 1-v operable max t pd of 1.7 ns at 1.8 v low power consumption, 10 a at 1.8 v 8-ma output drive at 1.8 v latch-up performance exceeds 100 ma per jesd 78, class ii esd protection exceeds jesd 22 ? 2000-v human-body model (a114-a) ? 200-v machine model (a115-a) ? 1000-v charged-device model (c101) description/ordering information this dual inverter is operational at 0.8-v to 2.7-v v cc , but is designed specifically for 1.65-v to 1.95-v v cc operation. the SN74AUC2G04 performs the boolean function y = a . nanostar ? and nanofree ? package technology is a major breakthrough in ic packaging concepts, using the die as the package. this device is fully specified for partial-power-down applications using i off . the i off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ordering information t a package ? orderable part number top-side marking ? ?40 c to 85 c nanostar ? ? wcsp (dsbga) 0.23-mm large bump ? yep tape and reel SN74AUC2G04yepr _ _ _uc_ ?40 c to 85 c nanofree ? ? wcsp (dsbga) 0.23-mm large bump ? yzp (pb-free) tape and reel SN74AUC2G04yzpr _ _ _uc_ sot (sot-23) ? dbv tape and reel SN74AUC2G04dbvr u04_ sot (sc-70) ? dck tape and reel SN74AUC2G04dckr uc_ ? package drawings, standard packing quantities, thermal data, symbolization, and pcb design guidelines are available at www.ti.com/sc/package. ? dbv/dck: the actual top-side marking has one additional character that designates the assembly/test site. yep/yzp: the actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. copyright ? 2003, texas instruments incorporated dbv or dck package (top view) 1 2 3 6 5 4 1a gnd 2a 1y v cc 2y 3 2 1 4 5 6 2a gnd 1a 2y v cc 1y yep or yzp package (bottom view) nanostar and nanofree are trademarks of texas instruments. please be aware that an important notice concerning avail ability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
SN74AUC2G04 dual inverter gate sces437a ? april 2003 ? revised june 2003 2 post office box 655303 ? dallas, texas 75265 function table (each inverter) input a output y h l l h logic diagram (positive logic) 1a 1y 16 2a 2y 34 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) ? supply voltage range, v cc ?0.5 v to 3.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range, v i (see note 1) ?0.5 v to 3.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . voltage range applied to any output in the high-impedance or power-off state, v o (see note 1) ?0.5 v to 3.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage range, v o (see note 1) ?0.5 v to v cc + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input clamp current, i ik (v i < 0) ?50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output clamp current, i ok (v o < 0) ?50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous output current, i o 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous current through v cc or gnd 100 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . package thermal impedance, ja (see note 2): dbv package 165 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dck package 258 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . yep/yzp package 123 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg ?65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated under ?recommended operating conditi ons? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. notes: 1. the input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are obser ved. 2. the package thermal impedance is calculated in accordance with jesd 51-7.
SN74AUC2G04 dual inverter gate sces437a ? april 2003 ? revised june 2003 3 post office box 655303 ? dallas, texas 75265 recommended operating conditions (see note 3) min max unit v cc supply voltage 0.8 2.7 v v high-level input voltage v cc = 0.8 v v cc v v ih high-level input voltage v cc = 1.1 v to 1.95 v 0.65 v cc v ih v cc = 2.3 v to 2.7 v 1.7 v low-level input voltage v cc = 0.8 v 0 v v il low-level input voltage v cc = 1.1 v to 1.95 v 0.35 v cc v il v cc = 2.3 v to 2.7 v 0.7 v i input voltage 0 3.6 v v o output voltage 0 v cc v i high-level output current v cc = 0.8 v ?0.7 ma i high-level output current v cc = 1.1 v ?3 ma i oh high-level output current v cc = 1.4 v ?5 ma oh v cc = 1.65 v ?8 v cc = 2.3 v ?9 i low-level output current v cc = 0.8 v 0.7 ma i low-level output current v cc = 1.1 v 3 ma i ol low-level output current v cc = 1.4 v 5 ma ol v cc = 1.65 v 8 v cc = 2.3 v 9 ? t/ ? v input transition rise or fall rate 20 ns/v t a operating free-air temperature ?40 85 c note 3: all unused inputs of the device must be held at v cc or gnd to ensure proper device operation. refer to the ti application report, implications of slow or floating cmos inputs , literature number scba004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions v cc min typ ? max unit v i oh = ?100 a 0.8 v to 2.7 v v cc ?0.1 v v i oh = ?0.7 ma 0.8 v 0.55 v v oh i oh = ?3 ma 1.1 v 0.8 v v oh i oh = ?5 ma 1.4 v 1 v i oh = ?8 ma 1.65 v 1.2 i oh = ?9 ma 2.3 v 1.8 v i ol = 100 a 0.8 v to 2.7 v 0.2 v v i ol = 0.7 ma 0.8 v 0.25 v v ol i ol = 3 ma 1.1 v 0.3 v v ol i ol = 5 ma 1.4 v 0.4 v i ol = 8 ma 1.65 v 0.45 i ol = 9 ma 2.3 v 0.6 i i a inputs v i = v cc or gnd 0 to 2.7 v 5 a i off v i or v o = 2.7 v 0 10 a i cc v i = v cc or gnd, i o = 0 0.8 v to 2.7 v 10 a c i v i = v cc or gnd 2.5 v 2.1 pf ? all typical values are at t a = 25 c.
SN74AUC2G04 dual inverter gate sces437a ? april 2003 ? revised june 2003 4 post office box 655303 ? dallas, texas 75265 switching characteristics over recommended operating free-air temperature range, c l = 15 pf (unless otherwise noted) (see figure 1) parameter from (input) to (output) v cc = 0.8 v v cc = 1.2 v 0.1 v v cc = 1.5 v 0.1 v v cc = 1.8 v 0.15 v v cc = 2.5 v 0.2 v unit parameter (input) (output) typ min max min max min typ max min max unit t pd a y 5.4 0.9 3.1 0.7 2 0.6 1 1.7 0.5 1.2 ns switching characteristics over recommended operating free-air temperature range, c l = 30 pf (unless otherwise noted) (see figure 1) parameter from (input) to (output) v cc = 1.8 v 0.15 v v cc = 2.5 v 0.2 v unit parameter (input) (output) min typ max min max unit t pd a y 0.8 1.3 2 0.7 1.5 ns operating characteristics, t a = 25 c parameter test v cc = 0.8 v v cc = 1.2 v v cc = 1.5 v v cc = 1.8 v v cc = 2.5 v unit parameter test conditions typ typ typ typ typ unit c pd power dissipation capacitance f = 10 mhz 12.5 12.5 12.5 12.5 14 pf
SN74AUC2G04 dual inverter gate sces437a ? april 2003 ? revised june 2003 5 post office box 655303 ? dallas, texas 75265 parameter measurement information v cc /2 t h t su from output under test c l (see note a) load circuit s1 2 v cc open gnd r l r l data input timing input v cc 0 v v cc 0 v 0 v t w input voltage waveforms setup and hold times voltage waveforms propagation delay times inverting and noninverting outputs voltage waveforms pulse duration t plh t phl t phl t plh v oh v oh v ol v ol v cc 0 v input output waveform 1 s1 at 2 v cc (see note b) output waveform 2 s1 at gnd (see note b) v ol v oh t pzl t pzh t plz t phz v cc 0 v v ol + v ? v oh ? v ? 0 v v cc voltage waveforms enable and disable times low- and high-level enabling output output t plh /t phl t plz /t pzl t phz /t pzh open 2 v cc gnd test s1 notes: a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. all input pulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 ? , slew rate 1 v/ns . d. the outputs are measured one at a time with one transition per measurement. e. t plz and t phz are the same as t dis . f. t pzl and t pzh are the same as t en . g. t plh and t phl are the same as t pd . h. all parameters and waveforms are not applicable to all devices. output control v cc /2 v cc /2 v cc /2 v cc /2 v cc /2 v cc /2 v cc /2 v cc /2 v cc /2 v cc /2 v cc /2 v cc /2 v cc v cc /2 v cc /2 0.8 v 1.2 v 0.1 v 1.5 v 0.1 v 1.8 v 0.15 v 2.5 v 0.2 v 1.8 v 0.15 v 2.5 v 0.2 v 2 k ? 2 k ? 2 k ? 2 k ? 2 k ? 1 k ? 500 ? v cc r l 0.1 v 0.1 v 0.1 v 0.15 v 0.15 v 0.15 v 0.15 v v ? c l 15 pf 15 pf 15 pf 15 pf 15 pf 30 pf 30 pf figure 1. load circuit and voltage waveforms
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) SN74AUC2G04dbvr active sot-23 dbv 6 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim SN74AUC2G04dbvre4 active sot-23 dbv 6 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim SN74AUC2G04dbvrg4 active sot-23 dbv 6 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim SN74AUC2G04dckr active sc70 dck 6 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim SN74AUC2G04dckre4 active sc70 dck 6 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim SN74AUC2G04dckrg4 active sc70 dck 6 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim SN74AUC2G04yzpr active wcsp yzp 6 3000 green (rohs & no sb/br) snagcu level-1-260c-unlim (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 4-may-2007 addendum-page 1
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant SN74AUC2G04dbvr sot-23 dbv 6 3000 180.0 9.2 3.23 3.17 1.37 4.0 8.0 q3 SN74AUC2G04dckr sc70 dck 6 3000 180.0 9.2 2.24 2.34 1.22 4.0 8.0 q3 package materials information www.ti.com 11-mar-2008 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) SN74AUC2G04dbvr sot-23 dbv 6 3000 202.0 201.0 28.0 SN74AUC2G04dckr sc70 dck 6 3000 202.0 201.0 28.0 package materials information www.ti.com 11-mar-2008 pack materials-page 2
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